This invention relates to a module for mounting a plurality of semiconductor devices (hereinafter referred to as LSI chips), and to a module substrate that interconnects the LSI chips.
A conventional example of a module substrate that interconnects a plurality of LSI chips (or simply referred to as chips) may be found in the U.S. Pat. No.4,302,625.
In this conventional example of a multi-layer ceramic substrate that interconnects LSI chips, testing and engineering pads are provided to the top surface on which the chips are mounted (simply referred to as the top surface of the substrate) and input/output pins and power supply pins are mounted to the underside of the substrate opposite to the chip-mounting surface (simply referred to as the underside of the substrate). This substrate also has a cooling means thermal-joined to the back of the chips to cool the chips.
In the above conventional module substrate, the testing and engineering change pads are arranged on the substrate surface around the circumference of the LSI chips in almost the same number as the chip input/output terminals. The penalty of this configuration is that in the LSI chips tending to have a greater number of terminals the package density of the chips must be made a sacrifice to secure the area for the testing and engineering change pads.
During module testing, a cooling means that is thermal-joined to the back of the chips must be removed to allow a testing probe to be connected to the testing and engineering change pads. And a special cooling system for testing that will not hinder the connection of the testing probe should be installed in place of the removed cooling means.
Recently, large computers employ chips with very high circuit integration of about 2000 gates per chip. They have high power consumption of 6W/chip and a large number of connecting points or joints of 160 points/chip. The trend for higher circuit integration of chips is notable, with the circuit density increasing three or four times in four years. It is therefore expected that in future computers there will be greater demands for chips with large power consumption and increased number of joints and that the conventional technique will reach a limit in (1) the cooling ability and (2) the number of joints and thus will not be able to cope with requirements for higher package density.